1. Field of Invention
The present invention relates to a computer system for data processing, and more particularly, to a computer system having a memory bridge configured in a processor socket to electrically connect a processor bus and a memory bus.
2. Related Art
The most significant component in a computer system is the CPU (Central Processing Unit), which is undoubtedly as important as a heart to a human. To precisely process data that becomes larger and more complex at a higher speed, several CPUs are configured on a mother board and/or an expansive CPU card to build up a multi-processor computer system. However, the mechanism of accessing memory still creates a bottleneck in high performance computing.
In a conventional system with south/north bridge architecture, memory accessing is controlled by a north bridge chip. As Shown in FIG. 1A, two processors 71 and 72 of a dual-processor system share a system memory 74, wherein the north bridge is utilized as a memory controller hub (MCH) 73. When only one of processor 71 and 72 is operating, almost all the system memory 74 is available. However, the accessing speed will be limited due to the control process of the MCH 73. And such situation becomes more obvious while the processor 71 and 72 are both operating and sharing the bandwidth of a memory bus between the MCH 73 and the system memory 74.
To solve the problem, cache memory is used to save common commands and data for CPU to access. No matter imbedded in the CPU or configured externally, the cache memory avoids the CPU from accessing system memory frequently and from slowing down the whole system. But for the system memory that managed by the MCH or north bridge, this sharing architecture is still a limitation itself.
Please refer to FIGS. 1B and 1C. In the illustrated four-processor system, each of the processor P0, P1, P2 and P3 has dedicated memory M0, M1, M2 and M3 respectively. The processor P0, P1, P2 and P3 connect each other by processor buses PB, and connect to an I/O controller IOC such as a south bridge or a PCI bridge by an I/O bus IOB. In each of the processor P0, P1, P2 and P3, a crossbar switch XBAR is configured to connect a Bus Port BP0, BP1 and BP2, and a memory controller MCT and a system request queue SRQ. The system request queue SRQ manages data processing requests for the processing core C while each memory controller MCT controls the accessing processes of the memory M0, M1, M2 and M3 through each memory bus MB. Under certain conditions, the memory accessing architecture shown in FIG. 1B provides higher accessing speed than the one shown in FIG. 1A, thereby allowing the processor P0, P1, P2 and P3 achieve the best performance. Furthermore, the processor P0, P1, P2 and P3 are capable of sharing memory M0, M1, M2 and M3 by way of processor buses PB and crossbar switch XBAR to reach optimum efficiency of memory utilization.
However, when one CPU fails in this multi-processor system, or one or more CPUs are removed by the user due to special reasons, those memories connected to the failed/removed will become unused. That is truly a waste.